1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a plurality of conductive lines in a memory cell array connected to a plurality of memory cells arranged in two adjacent column directions, respectively.
2. Description of the Background Art
Attention is paid to an NROM (Nitride Read Only Memory) type flash EEPROM (to be referred to as xe2x80x9cNROMxe2x80x9d hereinafter) which is a kind of a flash EEPROM among nonvolatile semiconductor memory devices. NROM is reported in U.S. Pat. Nos. 6,011,725 and 6,201,737.
FIG. 23 is a circuit diagram showing the configuration of the memory cell array of a conventional nonvolatile semiconductor memory device.
Referring to FIG. 23, the memory cell array includes a plurality of nonvolatile memory cells MC, a plurality of bit lines BL and a plurality of word lines WL.
Plural word lines WL and plural bit lines BL are arranged in row and column directions, respectively.
Each of plural nonvolatile memory cells MC is arranged to correspond to the intersection between word line WL and bit lie BL. Plural nonvolatile memory cells MC arranged in the same row are connected in series and the gates thereof are connected to same word line WL. Each bit line BL is arranged to pass through the connection point between two adjacent nonvolatile memory cells MC.
Nonvolatile memory cell MC includes two storage regions L1 and L2.
Data write and read operations for wiring and reading data to and from storage regions L1 and L2 of nonvolatile memory cell MC will next be described.
FIGS. 24A to 24D are views showing the data write or read operation for writing or reading data to and from the two storage regions in nonvolatile memory cell MC.
Referring to FIG. 24A, the gate of nonvolatile memory cell MC is connected to word line WL. Nonvolatile memory cell MC is assumed to be connected to bit lines BL0 and BL1. Nonvolatile memory cell MC has storage region L1 on a bit line BL0 side and storage region L2 on a bit line BL1 side as shown in FIG. 24C.
The write operation for writing data to storage region L1 will first be described. Referring to FIG. 24A, if data is to be written to storage region L1, the potential of bit line BL0 is kept to be a write potential VCCW and that of bit line BL1 is kept to be a ground potential GND. As a result, a write current Ifw is carried from bit line BL0 to bit line BL1 through nonvolatile memory cell MC. At this moment, data is written to storage region L1. Such a write operation for writing data to storage region L1 in nonvolatile memory cell MC will be referred to as xe2x80x9cforward writexe2x80x9d.
Next, the read operation for reading data from storage region L1 will be described. Referring to FIG. 24B, if data is to be read from storage region L1, the potential of bit line BL0 is kept to be ground potential GND and that of bit line BL1 is kept to be read potential VCCR. As a result, a read current Ifr is carried from bit line BL1 to bit line BL0. At this moment, data is read from storage region L1. Such a read operation for reading data from storage region L1 in nonvolatile memory cell MC will be referred to as xe2x80x9cforward readxe2x80x9d.
As can be seen, the direction of the current flowing during the write operation is opposite to that of the current flowing during the read operation in storage region L1.
The write operation for writing data to storage region L2 will next be described. Referring to FIG. 24C, if data is to be written to storage region L2, the potential of bit line BL0 is kept to be ground potential GND and that of bit line BL1 is kept to be write potential VCCW. As a result, a write current Irw is carried from bit line BL1 to bit line BL0. At this moment, data is written to storage region L2. Such a write operation for writing data to storage region L2 in nonvolatile memory cell MC will be referred to as xe2x80x9creverse writexe2x80x9d.
Next, the read operation for reading data from storage region L2 will be described. Referring to FIG. 24D, if data is to be read from storage region L2, the potential of bit line BL0 is kept to be read potential VCCR and that of bit line BL1 is kept to be ground potential GND. As a result, a read current Irr is carried from bit line BL0 to bit line BL1. At this moment, data is read from storage region L2. Such a read operation for reading data from storage region L2 in nonvolatile memory cell MC will be referred to as xe2x80x9creverse readxe2x80x9d.
As can be seen, the direction of the current flowing during the write operation is opposite to that of the current flowing during the read operation in storage region L2 as in the case of storage region L1. Further, the direction of the current flowing during the write operation for writing data to storage region L1 is opposite to that of the current flowing during the write operation for writing data to storage region L2. Likewise, the direction of the current during the read operation for reading data from storage region L1 is opposite to that of the current flowing during the read operation for reading data from storage region L2.
Therefore, it is important to control the potentials of respective bit lines BL during the write operation of NROM.
However, U.S. Pat. Nos. 6,011,725 and 6,201,737 fail to describe the peripheral circuits of a memory cell array which control the potentials of respective bit lines BL.
In addition, in flash EEPROM represented by NROM, the bit lines are formed, as diffused bit lines, on the main surface of a semiconductor substrate.
FIG. 25 is a plan view of conventional flash EEPROM.
Referring to FIG. 25, the nonvolatile semiconductor memory device has a plurality of bit lines BL arranged in a column direction. Plural bit lines BL are diffused bit lines formed on the main surface of the semiconductor substrate. Plural word lines WL are arranged in a row direction on plural bit lines BL. A plurality of metal wirings ML are arranged in the column direction on plural word lines WL. Plural metal wirings ML are arranged to correspond to plural bit lines BL, respectively and corresponding metal wiring ML and bit line BL are connected to each other through a plurality of contact sections 20.
FIG. 26 is a cross-sectional view taken along line XXVIxe2x80x94XXVI of FIG. 25.
Referring to FIG. 26, an n type diffused region 22 is formed on the main surface of a semiconductor substrate 21. This n type diffused region 22 corresponds to bit line BL shown in FIG. 25.
On the main surface of semiconductor substrate 21, insulating films 23a to 23d are formed at predetermined intervals. A word line WL1 is formed on insulating film 23a. A word line WL2 is formed on insulating film 23b. A word line WL3 is formed on insulating film 23c. A word line WL4 is formed on insulating film 23d. Word lines WL1 to WL4 are formed out of, for example, silicon.
On the main surface of semiconductor substrate 21, an interlayer insulating film 24 is formed in a region located on n type diffused region 22 on word lines WL1 to WL4 on the main surface of semiconductor substrate 21. Metal wiring ML is formed on interlayer insulating film 24.
Contact holes 25a and 25b are formed in a region located between insulating films 23b and 23c on n type diffused region 22. The surface of n type diffused region 22 is exposed to the bottom of each of contact holes 25a and 25b. Metal wiring ML is extended to the respective bottoms of contact holes 25a and 25b and connected to n type diffused region 22.
FIG. 27 is an explanatory view for a write operation for writing data to a nonvolatile memory cell in the memory cell array shown in FIG. 23.
Referring to FIG. 27, a case where H-level data is written to storage region L1 of a nonvolatile memory cell MC1 shown therein will be described.
Word line WL1 is selected, the potential of bit line BL0 is kept to write potential VCCW and that of bit lie BL2 is kept to be ground potential GND. In nonvolatile memory cell MC1, therefore, write current Ifw is carried from a node connected to bit line BL1 to a node connected to bit line BL2. As a result, data is written to storage region L1.
At this moment, when attention is paid to a nonvolatile memory cell MC0 adjacent nonvolatile memory cell MC1, an unnecessary current I1 is carried to nonvolatile memory cell MC0 if the potential of bit line BL0 is lower than that of bit line BL1. Unnecessary current I1 may possibly not only prevent power saving but also cause the memory cell array to malfunction.
Furthermore, according to the conventional art, data of 1 bit can be written to a memory cell at one time in the nonvolatile semiconductor memory device represented by NROM and throughput is thereby disadvantageously low.
Moreover, the nonvolatile semiconductor memory device having the cross section shown in FIG. 26 has the following disadvantages.
In semiconductor memory device manufacturing steps, plural word lines WL are normally formed at predetermined intervals. As shown in FIG. 26, however, if it is necessary to form contact holes 25a and 25b, contact holes 25a and 25b should be formed in a region in which word lines WL would be normally formed. This makes it impossible to secure the continuity of the shapes of a plurality of word lines.
In this case, word lines WL2 and WL3 shown in FIG. 26 may possibly be formed differently from other plural word lines WL, with the result that manufacturing irregularity occurs. To prevent such manufacturing irregularity, there is proposed a method of forming dummy word lines WLD1 and WLD2 between word lines WL2 and WL3 as shown in FIG. 27. If such dummy word lines are formed, the stability of the manufacturing steps of the semiconductor memory device. On the other hand, however, the area of the memory cell array increases.
In addition, although resistance can be decreased by connecting metal wiring ML to bit line BL through contact holes 25a and 25b, the conductivity depends on the diameters of contact holes 25a and 25b. Besides, as the contact holes are longer, the probability of causing poor opening under some influence increases.
It is an object of the present invention to provide a semiconductor memory device capable of suppressing a current which unnecessarily occurs during data write. It is another object of the present invention to provide a semiconductor memory device capable of improving throughput.
It is another object of the present invention to provide a semiconductor memory device capable of obtaining a low resistance of a bit line.
It is further another object of the present invention to provide a semiconductor memory device capable of reducing an area of a memory cell array.
A semiconductor memory device according to the present invention includes: a plurality of word lines; a plurality of bit lines; a plurality of memory cells; a plurality of potential supply lines; and a potential control circuit. A plurality of word lines are arranged in a row direction. A plurality of bit lines are arranged in a column direction. A plurality of memory cells are arranged in the row direction and the column direction. A plurality of potential supply lines are connected to a plurality of corresponding bit lines among the plurality of bit lines, respectively. A potential control circuit supplies a plurality of predetermined potentials corresponding to the plurality of bit lines through the plurality of potential supply lines, respectively. Each of the plurality of bit lines is connected to the plurality of memory cells arranged in the two adjacent columns.
As a result, even with a memory cell array structure in which the two adjacent memory cells are connected to a common bit line, write and read operations can be conducted to selected memory cells.
A semiconductor memory device according to the present invention includes: a plurality of memory cell array blocks; and a plurality of potential control circuits. A plurality of memory cell array blocks are arranged in a column direction. A plurality of potential control circuits are arranged in the column direction to correspond to the plurality of memory cell array blocks, respectively. Each of the plurality of memory cell array blocks includes: a plurality of word lines arranged in a row direction; a plurality of bit lines arranged in the column direction; and a plurality of memory cells arranged in the row direction and the column direction. The plurality of memory cells arranged in the row directions are connected in series and gates of the plurality of memory cells are connected to the word lines arranged in the row direction, respectively. Each of the plurality of bit lines is connected to two adjacent memory cells arranged in the column direction. Each of the potential control circuit supplies a first predetermined potential to a first bit line connected to a selected memory cell and supplies a second predetermined potential to a second bit line, among the plurality of bit lines in the corresponding memory cell array block. Another potential control circuit adjacent the potential control circuit supplies the second predetermined potential to the first bit line and supplies the first predetermined potential to the second bit line in the corresponding memory cell array block.
As a result, it is possible to simultaneously conduct write and read operations to a plurality of memory cells. Throughput is thereby improved. In addition, the flow of an unnecessary current carried between the selected memory cells can be prevented.
A semiconductor memory device according to the present invention is a semiconductor memory device including a first conductive type semiconductor substrate having a main surface and a memory cell array. The memory cell array includes: a plurality of conductive layers of a second conductive type; a plurality of word lines; a plurality of conductive lines; a plurality of conductive layers of a second conductive type formed on the main surface of the semiconductor substrate, and arranged in a column direction; a plurality of memory cells; and a plurality of pile driving sections. A plurality of word lines are arranged in a row direction. A plurality of conductive lines are formed on an upper layer of the plurality of word lines, arranged in the column direction, and each includes a plurality of conductive segments. A plurality of memory cells are arranged to correspond to intersections between the word lines and the conductive lines, respectively. A plurality of pile driving sections are formed on the conductive layers, respectively. Each of the plurality of pile driving sections includes: a second conductive layer formed on each of the conductive layers on the main surface of the semiconductor substrate; and a plurality of contact sections formed between the second conductive layer and the conductive segments.
Therefore, according to conventional semiconductor memory device manufacturing steps, it is impossible to secure the continuity of the shapes of a plurality of word lines. However, by inserting the pile driving sections, it is possible to secure the continuity of the shapes of the word lines. It is, therefore, unnecessary to form a dummy word line or the like. Furthermore, since the pile driving sections are formed on the diffused bit lines formed on the main surface of the semiconductor substrate, respectively, it is possible to decrease resistance. Moreover, since the presence of the pile driving sections enables shortening the length of each contact hole compared with that of the conventional contact hole, the probability of causing the poor opening of the contact holes in the manufacturing steps is greatly decreased and manufacturing irregularity is decreased. In addition, since the contact can be shortened and the resistance is decreased by the presence of the pile driving sections, the contact can be made small in size and a layout margin increases, accordingly. Therefore, it is possible to form a plurality of contacts in the same region compared with the conventional method. Consequently, even if one of the contacts formed in the same region causes poor opening under some influence, it is possible to secure the opening by the other contacts. As a result, it is possible to improve yield.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.